Normal basis of finite GF(2:OSm:OE)
IEEE Transactions on Information Theory
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
Elliptic curves in cryptography
Elliptic curves in cryptography
Itoh-Tsujii Inversion in Standard Basis and Its Application in Cryptography and Codes
Designs, Codes and Cryptography
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
IEEE Transactions on Computers
Efficient Finite Field Serial/Parallel Multiplication
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m)
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
A fast digit-serial systolic multiplier for finite field GF(2m)
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials
IEEE Transactions on Computers
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Fast VLSI arithmetic algorithms for high-security elliptic curve cryptographic applications
IEEE Transactions on Consumer Electronics
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Extended sequential logic for synchronous circuit optimization and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Low latency systolic montgomery multiplier for finite field GF(2m) based on pentanomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Finite field accumulation is the simplest of all the finite field operations, but at the same time, it is one of the most frequently encountered operations in finite field arithmetic. In this paper, we present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF(2m). The critical path, as well as, the hardwarecomplexity are reduced in the proposed design by performing the accumulation operation using m number of T flip-flops instead of using a combination of m number of XOR gates with equal number of D flip-flops in dependent loop structures. The conventional design is found to involve nearly 39% more area, 53% more delay, and 40% more maximum ac power consumption compared with the proposed accumulator. The proposed finite field accumulator is used further for the implementation of serial/parallel polynomial-basis finite field multiplication and bit-serial interconversion between polynomial basis representation and normal basis representation over GF(2m). The area-time complexity of the proposed bit-serial/parallel multiplier is less than half of the best of the corresponding existing structures. The structure proposed for digit-serial/ parallel multiplication for trinomials is found to involve nearly 56% less area-time complexity compared with the best of the corresponding existing multipliers; and the existing design of bit-serial basis conversion is found to involve nearly twice area-time complexity compared with the proposed design using the proposed finite field accumulator.