Complexity analysis of finite field digit serial multipliers on FPGAs

Authors:
Gang Zhou;Li Li;Harald Michalik
Affiliations:
Institute of Computer and Network Engineering, Technical University of Braunschweig, Germany;Institute of Computer and Network Engineering, Technical University of Braunschweig, Germany;Institute of Computer and Network Engineering, Technical University of Braunschweig, Germany
Venue:
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Year:
2012

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Abstract

This paper presents the complexity analysis of digit serial finite field multipliers over GF(2m) on FPGAs. Instead of discussing the complexity by using AND and XOR gates as primitives, we present the complexity analysis directly based on FPGA primitives, e.g., Look-Up-Tables (LUTs). Given digit size d, the number of LUTs and the level of LUT delay are estimated. The previous ASIC based complexity analysis shows the optimum digit size (for Area-Time-Product) is 2l−1. We show in this work that the optimum digit sizes are different on FPGAs. They are those digits ds which satisfy ⌈m/{d-1}⌉ ≠ ⌈ m/d ⌉. We also validate our analysis with experimental results on GF(2163) and GF(2233).