Low complexity digit serial systolic montgomery multipliers for special class of GF(2m)

Authors:
Somsubhra Talapatra;Hafizur Rahaman;Jimson Mathew
Affiliations:
Department of Information Technology, Bengal Engineering and Science University, Shibpur, India;Department of Information Technology, Bengal Engineering and Science University, Shibpur, India;Department of Computer Science, University of Bristol, Bristol, UK
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since tbe systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ⌈m/L⌉, m is the word size and L is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.