A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)

Authors:
M. Sudhakar;R. V. Kamala;M. B. Srinivas
Affiliations:
International Institute of Information Technology, Hyderabad, Andhra Pradesh, India;International Institute of Information Technology, Hyderabad, Andhra Pradesh, India;International Institute of Information Technology, Hyderabad, Andhra Pradesh, India
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

This paper proposes a unified and reconfigurable Montgomery multiplier architecture which can operate in both primary GF(p) and binary extension fields GF(2^n). The multiplier provides efficient execution of Montgomery multiplication in either field for different operand lengths. It supports any operand length 'n', 1\le n \le N where the upper value of N is application dependent. The final result is obtained in 'n+2' clock cycles for either field. Propagation delay of the design is investigated and found to be comparable with the existing unified multiplier architectures while providing reconfigurability at the same time. The proposed architecture has high order of flexibility and low hardware complexity with critical path delay independent of operand length. The multiplier can find application in, for example, Elliptic curve cryptographic(ECC) processors.