Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Improved Algorithms for Elliptic Curve Arithmetic in GF(2n)
SAC '98 Proceedings of the Selected Areas in Cryptography
Software Implementation of Elliptic Curve Cryptography over Binary Fields
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
FPGA Montgomery Multiplier Architectures - A Comparison
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA
Proceedings of the 20th annual conference on Integrated circuits and systems design
Parallelized radix-4 scalable montgomery multipliers
Proceedings of the 20th annual conference on Integrated circuits and systems design
New and improved architectures for Montgomery modular multiplication
Mobile Networks and Applications
Computers and Electrical Engineering
Low complexity digit serial systolic montgomery multipliers for special class of GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New directions in cryptography
IEEE Transactions on Information Theory
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Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GF(2^m), is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. FPGAs allow the implementation of this kind of algorithms in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for constructing GF(2^m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) and study their area-performance trade-offs. Different Montgomery multipliers were implemented using several digits and finite fields to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to show suitable configurations for ECC implementations using NIST recommended parameters. The results achieved show a notable improvement against FPGA Montgomery multiplier previously reported, achieving the highest throughput and the best efficiency.