An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography

Authors:
Miguel Morales-Sandoval;Claudia Feregrino-Uribe;René Cumplido;Ignacio Algredo-Badillo
Affiliations:
Computer Science Department, National Institute for Astrophysics, Optics and Electronics, Luis Enrique Erro No. 1, Tonantzintla, Pue. 72840, Mexico;Computer Science Department, National Institute for Astrophysics, Optics and Electronics, Luis Enrique Erro No. 1, Tonantzintla, Pue. 72840, Mexico;Computer Science Department, National Institute for Astrophysics, Optics and Electronics, Luis Enrique Erro No. 1, Tonantzintla, Pue. 72840, Mexico;Computer Science Department, National Institute for Astrophysics, Optics and Electronics, Luis Enrique Erro No. 1, Tonantzintla, Pue. 72840, Mexico
Venue:
Computers and Electrical Engineering
Year:
2009

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Abstract

A hardware architecture for GF(2^m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.