Parallelized radix-4 scalable montgomery multipliers

Authors:
Nathaniel Ross Pinckney;David Money Harris
Affiliations:
Harvey Mudd College, Claremont, CA;Harvey Mudd College, Claremont, CA
Venue:
Proceedings of the 20th annual conference on Integrated circuits and systems design
Year:
2007

Citing 5
Cited 2

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Abstract

This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. The design does not require hardware multipliers, and uses parallelized multiplication to shorten the critical path. By left-shifting the sources rather than right-shifting the result, the latency between processing elements is shortened from two cycles to nearly one. The new design can perform 1024-bit modular exponentiation in 8.7 ms and 256-bit exponentiation in 0.36 ms using 5916 Virtex2 4-input lookup tables. This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones.