Very High Radix Scalable Montgomery Multipliers

Authors:
Kyle Kelley;David Harris
Affiliations:
Harvey Mudd College;Harvey Mudd College
Venue:
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Year:
2005

Citing 0
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Abstract

This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w 脳 v-bit integer multipliers in place of AND gates. The new design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 x 16 multipliers, making it the fastest scalable design yet reported.