Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Architectures for exponentiation in GF (2n)
Proceedings on Advances in cryptology---CRYPTO '86
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
IEEE Transactions on Computers
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Low Power Digital CMOS Design
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Efficient Finite Field Serial/Parallel Multiplication
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m)
ITCC '03 Proceedings of the International Conference on Information Technology: Computers and Communications
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m)
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
LFSR multipliers over GF(2m) defined by all-one polynomial
Integration, the VLSI Journal
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm
Integration, the VLSI Journal
Improved throughput bit-serial multiplier for GF(2m) fields
Integration, the VLSI Journal
A New 40-nm FPGA and ASIC Common Platform
IEEE Micro
Finite Fields: Theory and Computation The Meeting Point of Number Theory, Computer Science, Coding Theory and Cryptography
Algorithm engineering for public key algorithms
IEEE Journal on Selected Areas in Communications
Secure Transmission of Mobile Agent in Dynamic Distributed Environments
Wireless Personal Communications: An International Journal
Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
Journal of Signal Processing Systems
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In this paper, a novel architecture for a versatile polynomial basis multiplier over GF(2^m) is presented. The proposed architecture provides an efficient execution of the Most Significant Bit (MSB)-First, bit-serial multiplication for different operand lengths. The main advantages of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) low power consumption by employing the gated clock technique (d) improvement of maximum clock frequency due to the lessening of critical path delay. These abilities are achieved by means of utilizing a row of tri-state buffers and some control signals along with the (MSB)-first multiplier in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity.