A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m)

Authors:
Markus Hütter;Johann Groβschädl;Guy-Armand Kamendje
Affiliations:
-;-;-
Venue:
ITCC '03 Proceedings of the International Conference on Information Technology: Computers and Communications
Year:
2003

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Abstract

We present an architecture for digit-serial multiplicationin finite fields GF(2m) with applications to cryptography.The proposed design uses polynomial basis representationand interleaves multiplication steps with degree reductionsteps. An M-bit multiplier works with arbitrary irreduciblepolynomials and can be used or any binary field of order2m \le 2M. We introduce a new method or degree reductionwhich is significantly faster than previously reported iterative techniques. A representative example or a digit-sizeof d = 4, illustrating the reduction circuit, is given. Experimental results show that the proposed method shortens thecritical path of the reduction circuit by a factor of between1.36 and 3.0 or digit-sizes ranging rom d = 4 to 16 .