Finite field for scientists and engineers
Finite field for scientists and engineers
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
IEEE Transactions on Computers
Elliptic Curve Public Key Cryptosystems
Elliptic Curve Public Key Cryptosystems
New directions in cryptography
IEEE Transactions on Information Theory
A public key cryptosystem and a signature scheme based on discrete logarithms
IEEE Transactions on Information Theory
Performance evaluation of highly efficient techniques for software implementation of LFSR
Computers and Electrical Engineering
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)
Integration, the VLSI Journal
Low-complexity multiplier for GF(2m) based on all-one polynomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
Journal of Signal Processing Systems
Information Processing Letters
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This paper presents two bit-serial modular multipliers based on the linear feedback shift register using an irreducible all one polynomial (AOP) over GF(2^m). First, a new multiplication algorithm and its architecture are proposed for the modular AB multiplication. Then a new algorithm and architecture for the modular AB^2 multiplication are derived based on the first multiplier. They have significantly smaller hardware complexity than the previous multipliers because of using the property of AOP. It simplifies the modular reduction compared with the case of using the generalized irreducible polynomial. Since the proposed multipliers have low hardware requirements and regular structures, they are suitable for VLSI implementation. The proposed multipliers can be used as the kernel architecture for the operations of exponentiation, inversion, and division.