Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Efficient finite field digital-serial multiplier architecture for cryptography applications
Proceedings of the conference on Design, automation and test in Europe
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Improved throughput bit-serial multiplier for GF(2m) fields
Integration, the VLSI Journal
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Journal of Signal Processing Systems
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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WILF'05 Proceedings of the 6th international conference on Fuzzy Logic and Applications
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)
Integration, the VLSI Journal
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Finite field has received a lot of attention due to its widespread applications in cryptography, coding theory, etc. Design of efficient finite field arithmetic architectures is very important and of great practical concern. In this paper, a new bit-serial/parallel finite field multiplier is presented with standard basis representation. This design is regular and well suited for VLSI implementation. As compared to existing serial/parallel finite field multipliers, it has smaller critical path, lower latency and can be easily pipelined. When it is used as a building block for large systems, it can achieve more savings in hardware in the broadcast structures by utilizing sub-structure sharing technique. This paper also presents two generalized algorithms for finite field serial/parallel multiplication. They can be used to derive efficient bit-parallel, digit-serial or bit-serial multiplication architectures. The optimal primitive polynomials over GF(2m) (for 2