Efficient finite field digital-serial multiplier architecture for cryptography applications

  • Authors:
  • G. Bertoni;L. Breveglieri;P. Fragneto

  • Affiliations:
  • Politechnico di Milano, P.zza L. Da Vinci n. 32, I-20133 Milano, Italy;Politechnico di Milano, P.zza L. Da Vinci n. 32, I-20133 Milano, Italy;ST Mircroelectronics Agrate Brianza(MI), Via Olivetti 2, I-20041 Agrate B., Italy

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2001

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Abstract