Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Efficient parallel multiplier in shifted polynomial basis
Journal of Systems Architecture: the EUROMICRO Journal
An efficient technique for synthesis and optimization of polynomials in GF(2m)
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields
IEEE Transactions on Computers
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme
IEEE Transactions on Computers
Concurrent error detection in Reed-Solomon encoders and decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields
WAIFI '08 Proceedings of the 2nd international workshop on Arithmetic of Finite Fields
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography
Theory of Quantum Computation, Communication, and Cryptography
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
Low complexity bit-parallel multipliers based on a class of irreducible pentanomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient bit-parallel multipliers over finite fields GF(2m)
Computers and Electrical Engineering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low complexity digit serial systolic montgomery multipliers for special class of GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a
Quantum Information & Computation
Explicit formulae of polynomial basis squarer for pentanomials using weakly dual basis
Integration, the VLSI Journal
VLSI performance evaluation and analysis of systolic and semisystolic finite field multipliers
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
VLSI architecture for bit parallel systolic multipliers for special class of GF(2m) using dual bases
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Integration, the VLSI Journal
Quantum binary field inversion: improved circuit depth via choice of basis representation
Quantum Information & Computation
New bit parallel multiplier with low space complexity for all irreducible trinomials over GF(2n)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient quantum circuits for binary elliptic curve arithmetic: reducing T-gate complexity
Quantum Information & Computation
Preserving Hamming Distance in Arithmetic and Logical Operations
Journal of Electronic Testing: Theory and Applications
New efficient bit-parallel polynomial basis multiplier for special pentanomials
Integration, the VLSI Journal
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Representing the field elements with respect to the polynomial (or standard) basis, we consider bit parallel architectures for multiplication over the finite field GF(2m). In this effect, first we derive a new formulation for polynomial basis multiplication in terms of the reduction matrix Q. The main advantage of this new formulation is that it can be used with any field defining irreducible polynomial. Using this formulation, we then develop a generalized architecture for the multiplier and analyze the time and gate complexities of the proposed multiplier as a function of degree m and the reduction matrix Q. To the best of our knowledge, this is the first time that these complexities are given in terms of Q. Unlike most other articles on bit parallel finite field multipliers, here we also consider the number of signals to be routed in hardware implementation and we show that, compared to the well-known Mastrovito's multiplier, the proposed architecture has fewer routed signals. The proposed generalized architecture is further optimized for three special types of polynomials, namely, equally spaced polynomials, trinomials, and pentanomials. We have obtained explicit formulas and complexities of the multipliers for these three special irreducible polynomials. This makes it very easy for a designer to implement the proposed multipliers using hardware description languages like VHDL and Verilog with minimum knowledge of finite field arithmetic.