IEEE Transactions on Computers
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers
IEEE Transactions on Computers
Five, Six, and Seven-Term Karatsuba-Like Formulae
IEEE Transactions on Computers
A Fast Implementation of Multiplicative Inversion Over GF(2^m )
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient FPGA-based karatsuba multipliers for polynomials over F2
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
An efficient high speed implementation of flexible characteristic-2 multipliers on FPGAs
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2m). By introducing the common expression sharing and the complexity analysis on odd-term polynomials, we achieve a lower gate bound than previous ASIC discussions. The analysis is extended by using 4-input/6-input lookup tables (LUT) on FPGAs. For an arbitrary bit-depth, the optimum iteration step is shown. The optimum iteration steps differ for ASICs, 4-input LUT-based FPGAs and 6-input LUT-based FPGAs. We evaluate the LUT complexity and area-time product tradeoffs on FPGAs with different computer-aided design (CAD) tools. Furthermore, the experimental results on FPGAs for bit parallel modular multipliers are shown and compared with previous implementations. To the best of our knowledge, our bit parallel multipliers consume the least resources among known FPGA implementations to date.