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In this paper, an efficient architecture for multiplicative inversion in GF(2^m ) using addition chains is presented. The approach followed was based on the Itoh-Tsujii algorithm targeting a fast implementation on reconfigurable hardware devices. We give the design details of the proposed architecture whose main building blocks are a field multi-squarer block, a field polynomial multiplier and a BRAM two-ports memory. Our design is able to compute multiplicative inversion in GF(2^{193} ) in about 1.33µS using only 27 clock cycles.