The accelerated integer GCD algorithm
ACM Transactions on Mathematical Software (TOMS)
Itoh-Tsujii Inversion in Standard Basis and Its Application in Cryptography and Codes
Designs, Codes and Cryptography
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A VLSI Algorithm for Modular Multiplication/Division
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
On the Hardware Design of an Elliptic Curve Cryptosystem
ENC '04 Proceedings of the Fifth Mexican International Conference in Computer Science
A Fast Implementation of Multiplicative Inversion Over GF(2^m )
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
FPGA and ASIC Implementation of ECC Processor for Security on Medical Embedded System
ICITA '05 Proceedings of the Third International Conference on Information Technology and Applications (ICITA'05) Volume 2 - Volume 02
A Carry-Free Architecture for Montgomery Inversion
IEEE Transactions on Computers
Secure Transmission of Mobile Agent in Dynamic Distributed Environments
Wireless Personal Communications: An International Journal
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GCD algorithm is a well known algorithm for computing modular division and inversion which is widely used in Elliptic Curve Cryptography (ECC). Also division is the most time-consuming operation in Elliptic and Hyperelliptic Curve Cryptography. The conventional radix-2 GCD algorithm, is performed modular division over GF(2m) in approximately 2m iterations (or clock cycles). These algorithms consist of at least four comparisons at each iteration. In this paper the conventional algorithm is extended to radix-4. To increase the efficiency of algorithm the number of comparisons is reduced. So the algorithm enables very fast computation of division over GF(2m). The proposed algorithm described in such a way that its hardware realization is straightforward. The implemented results show reducing the division time to m clock cycles. Also the proposed architecture is compared with other reported dividers and it has been shown that the proposed architecture only occupies %14 more LUT (over GF(2163)) while the computation time is decreased to half.