VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
VLSI array processors
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Error control systems for digital communication and storage
Error control systems for digital communication and storage
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Cryptography and network security (2nd ed.): principles and practice
Cryptography and network security (2nd ed.): principles and practice
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Double-Basis Multiplicative Inversion Over GF(2m)
IEEE Transactions on Computers
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
An efficient technique for synthesis and optimization of polynomials in GF(2m)
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields
IEEE Transactions on Computers
IEEE Transactions on Computers
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Collision Search for Elliptic Curve Discrete Logarithm over GF(2m) with FPGA
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
High speed modular divider based on GCD algorithm
ICICS'07 Proceedings of the 9th international conference on Information and communications security
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test generation in systolic architecture for multiplication over GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract--We extend the binary algorithm invented by Stein and propose novel iterative division algorithms over {\rm GF}(2^m) for systolic VLSI realization. While Algorithm EBg is a basic prototype with guaranteed convergence in at most 2m-1 iterations, its variants, Algorithms EBd and EBdf, are designed for reduced complexity and fixed critical path delay, respectively. We show that Algorithms EBd and EBdf can be mapped to parallel-in parallel-out systolic circuits with low area-time complexities of {\rm O}(m^2\log\log m) and {\rm O}(m^2), respectively. Compared to the systolic designs based on the extended Euclid's algorithm, our circuits exhibit significant speed and area advantages.