Introduction to finite fields and their applications
Introduction to finite fields and their applications
Optimal-time multipliers and C-testability
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Constant testability of combinational cellular tree structures
Journal of Electronic Testing: Theory and Applications
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Fast Algorithms for Digital Signal Processing
Fast Algorithms for Digital Signal Processing
Error-Control Coding for Data Networks
Error-Control Coding for Data Networks
VLSI Designs for Multiplication over Finite Fields GF (2m)
AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Theory of Galois Switching Functions
IEEE Transactions on Computers
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
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We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.