Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)
IEEE Transactions on Computers
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This paper presents a testability enhancement technique suited for AND-EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set. Both cascaded and tree implementations of the EXOR-part are considered. The AND-EXOR based circuit implemented with a cascaded EXOR-part requires a universal test set of size (2n+6) for an n-variable function implementation. For Generalized Reed-Muller (GRM) implementation, this test set detects all single stuck-at and bridging faults (both OR-type and AND-type) and also large number of multiple bridging faults. For an Exclusive-OR Sum-of-Products (ESOP) implementation, a few single bridging faults may remain untested under this test set, occurrence of which can be minimized by employing an appropriate design and layout technique. Next, it is shown that an AND-EXOR network with a tree-based EXOR-part can be tested for similar faults by a universal test set of size (2n+8). This paper also solves an open problem of designing a universal test for a tree-based AND-EXOR circuit. Since the EXOR-tree has depth of (@?log"2s@?+1), where s is the number of product terms in the given AND-EXOR expression, this tree-based design reduces the circuit delay significantly compared to cascaded EXOR implementation. In both the cases, the test set can be stored in a ROM on-chip for built-in self-test (BIST) purposes. For several benchmark circuits, the universal test set is found to be much smaller in size than the ATPG-generated test sets.