Logic testing and design for testability
Logic testing and design for testability
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Fault Detection in Combinational Networks by Reed-Muller Transforms
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
Logic Synthesis and Optimization
Logic Synthesis and Optimization
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
Fault Models for Quantum Mechanical Switching Networks
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an $n$ input circuit is ($n+6$). For Built-in Self-Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudorandom pattern and that it provides 100 percent single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudoexhaustive or pseudorandom test set.