Fault Detection in Combinational Networks by Reed-Muller Transforms
IEEE Transactions on Computers
Interpolation and approximation of sparse multivariate polynomials over GF(2)
SIAM Journal on Computing
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Generalized Transforms for Multiple Valued Circuits and Their Fault Detection
IEEE Transactions on Computers
Constant depth circuits, Fourier transform, and learnability
Journal of the ACM (JACM)
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Note on the Polynomial Form of Boolean Functions and Related Topics
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields
IEEE Transactions on Computers
Identifying redundant gate replacements in verification by error modeling
Proceedings of the IEEE International Test Conference 2001
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
ATS '98 Proceedings of the 7th Asian Test Symposium
Identifying Redundant Wire Replacements for Synthesis and Verification
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An efficient filter-based approach for combinational verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realization-independent ATPG for designs with unimplemented blocks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields
IEEE Transactions on Computers
Fault tolerant glucose sensor readout and recalibration
Proceedings of the 2nd Conference on Wireless Health
| Hi-index | 14.98 |
In this paper, we investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the Arithmetic Transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the Universal Test Set (UTS) approach to test vector generation. The major result in this paper shows that, for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n^{log t}_2). Consequently, verification confidence can be parameterized by the size of the error t, where at most O(n^{log t}_2) verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the Arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.