Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
A Fortran language system for mutation-based software testing
Software—Practice & Experience
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An experimental determination of sufficient mutant operators
ACM Transactions on Software Engineering and Methodology (TOSEM)
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Formal Verification of Hardware Design
Formal Verification of Hardware Design
Prototyping the M68060 for Concurrent Verification
IEEE Design & Test
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Journal of Symbolic Computation
Identifying Redundant Wire Replacements for Synthesis and Verification
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Error Diagnosis of Sequential Circuits Using Region-Based Model
Journal of Electronic Testing: Theory and Applications
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Fast co-verification of HDL models
Microelectronic Engineering
Understanding bug fix patterns in verilog
Proceedings of the 2008 international working conference on Mining software repositories
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generation of TLM testbenches using mutation testing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A design verification methodology for microprocessor hardware based on modeling design errors and generating simulation vectors for the modeled errors via physical fault testing techniques is presented. We have systematically collected design error data from a number of microprocessor design projects. The error data is used to derive error models suitable for design verification testing. A class of basic error models is identified and shown to yield tests that provide good coverage of common error types. To improve coverage for more complex errors, a new class of conditional error models is introduced. An experiment to evaluate the effectiveness of our methodology is presented. Single actual design errors are injected into a correct design, and it is determined if the methodology will generate a test that detects the actual errors. The experiment has been conducted for two microprocessor designs and the results indicate that very high coverage of actual design errors can be obtained with test sets that are complete for a small number of synthetic error models.