The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
ATS '98 Proceedings of the 7th Asian Test Symposium
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An efficient filter-based approach for combinational verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identifying Redundant Wire Replacements for Synthesis and Verification
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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This paper considers verification of combinational circuits bytest vectors under assumption of gate and wire replacementfaults. Identifying redundant faults is critical to the quality andspeed of such verification schemes. We propose the first knownexact redundancy identification of gate replacement faults,together with its efficient approximations. While both solutionsuse the SAT formulation of redundancy identification, wepropose the means to effectively use any single stuck-at-valueredundancy identification in the approximate schemes, withvarying detection accuracy. Critical to the latter are the noveluses of don't care approximations that detect many redundantfaults and quickly identify those that can be detected by methodsfor stuck-at value faults. Test generation scheme that uses theerror-correcting properties of Arithmetic Transform isincorporated into the overall verification procedure, and isshown to provide high fault coverage for these fault models.