The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Improved alternative wiring scheme applying dominator relationship
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Design rewiring based on diagnosis techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the means to effectively use any single stuck-at-value redundancy identification in the approximate schemes. In the latter, we employ the novel use of don't care approximations that detect many redundant faults and quickly identify those that can be detected by stuck-at value identifications. A test generation scheme that uses the error-correcting properties of Arithmetic Transform is incorporated into the overall verification procedure. The test set provides high fault coverage.