High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MP3: The Definitive Guide
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
This paper presents a novel technique for extending the capacity of trace buffers when capturing debug data during post-silicon debug. It exploits the fact that is it not necessary to capture error-free data in the trace buffer since that information can be obtained from simulation. A selective data capture method is proposed in this paper that only captures debug data during clock cycles in which errors are present. The proposed debug method requires only three debug sessions. The first session estimates a rough error rate, the second session identifies a set of suspect clock cycles where errors may be present, and the third session captures the suspect clock cycles in the trace buffer. The suspect clock cycles are determined through a 2-D compaction technique using multiple-input signature register signatures and cycling register signatures. Intersecting both signatures generates a small number of suspect clock cycles for which the trace buffer needs to capture. The effective observation window of the trace buffer can be expanded significantly, by up to orders of magnitude. Experimental results indicate very significant increases in the effective observation window for a trace buffer can be obtained.