Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A reverse-encoding-based on-chip bus tracer for efficient circular-buffer utilization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Trace buffers are commonly used to capture data during in-system silicon debug. This paper exploits the fact that it is not necessary to capture error-free data in the trace buffer since that information is obtainable from simulation. The trace buffer need only capture data during clock cycles in which errors are present. A three pass methodology is proposed. During the first pass, the rough error rate is measured, in the second pass, a set of suspect clock cycles where errors may be present is determined, and then in the third pass, the trace buffer captures only during the suspect clock cycles. In this manner, the effective observation window of the trace buffer can be expanded significantly, by up to orders of magnitude. This greatly increases the effectiveness of a given size trace buffer and can rapidly speed up the debug process. The suspect clock cycles are determined through a two dimensional (2-D) compaction technique using a combination of multiple-input signature register (MISR) signatures and cycling register signatures. By intersecting the signatures, the proposed 2-D compaction technique generates a small set of remaining suspect clock cycles for which the trace buffer needs to capture data. Experimental results indicate very significant increases in the effective observation window for a trace buffer can be obtained.