On-chip dynamic signal sequence slicing for efficient post-silicon debugging

Authors:
Yeonbok Lee;Takeshi Matsumoto;Masahiro Fujita
Affiliations:
The University of Tokyo;The University of Tokyo;The University of Tokyo
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

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Abstract

In post-silicon debugging, low observability of internal signal values and large amount of traces are considered as the most critical problems. To address these problems, we propose an on-chip circuitry named DSC (Dynamic Slicing Circuit) which outputs the input signal values that actually influence on an erroneous output value in a particular execution of a chip by analyzing dependencies among signals. Since such input signal values are usually a small subset of the entire input sequence, we can reproduce the error by simulation using them. To realize DSC, we propose a variable named d-tag (Dependency Tag) representing dependency of a signal value with respect to another signal value. For demonstrating our method, we prepared three design examples and implemented DSC circuits on them. As a result, we could successfully extract input signal values that influenced the target output value from a number of random input sequence, for every case. We observed that the number of the extracted input values was significantly smaller than that of the original sequence. The area overhead for DSC circuit were also practical, 4% in average.