File System Interfaces for Embedded Software Development
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Embedded software debugging using virtual filesystem abstractions
Journal of Systems Architecture: the EUROMICRO Journal
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
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To enable efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for controlling multiple IEEE 1149.1 compliant debug interfaces on a single system chip. The presented architecture is fully compliant with the IEEE only the chip-level debug and boundary scan hardware, but also whether or not the bypass multiplexer is activated. When the chip-level TAP support are also presented to allow multiple debugger tools to control debug operations in multiple heterogeneous cores via this architecture. As an experiment, the proposed architecture is mapped on an FPGA to verify concurrent debug of multiple cores.