IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pruning-based trace signal selection algorithm
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RATS: restoration-aware trace signal selection for post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-silicon debugging of PMU integration errors using behavioral models
Integration, the VLSI Journal
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
| Hi-index | 0.00 |
Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, designers can only afford to trace a small number of signals in the design due to the associated overhead. Selecting which signals to trace is therefore a crucial issue for the effectiveness of this technique. This paper proposes an automated trace signal selection strategy that is able to dramatically enhance the visibility in post-silicon validation. Experimental results on benchmark circuits show that the proposed technique is more effective than existing solutions.