Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Case Study on Speed Failure Causes in a Microprocessor
IEEE Design & Test
Automated Selection of Signals to Observe for Efficient Silicon Debug
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing "signal selection" algorithms to further increase the logic restorability inside the chip. In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric. Based on this observation, we propose a procedure which biases the selection to increase the restorability of a desired set of critical state elements, without sacrificing the (overall) logic visibility. We propose to select the critical state elements to increase the "timing visibility" inside the chip to facilitate the debugging of timing errors which are perhaps the most challenging type of error to debug at the post-silicon stage. Specifically, we introduce a case when the critical state elements are selected to track the transient fluctuations in the power delivery network which can cause significant variations in the delays of the speedpaths in the circuit in nanometer technologies. This paper proposes to use the trace buffer technology to increase the timing visibility inside the chip, without sacrificing the logic visibility.