A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Trace Signal Selection for Post Silicon Validation and Debug
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The main challenge in post-silicon debug is the lack of observability to the internal signals of a chip. Trace buffer technology provides one venue to address this challenge by online tracing of a few selected state elements. Due to the limited bandwidth of the trace buffer, only a few state elements can be selected for tracing. Recent research has focused on automated trace signal selection problem in order to maximize restoration of the untraced state elements using the few traced signals. Existing techniques can be categorized into high quality but slow "simulation-based", and lower quality but much faster "metric-based" techniques. This work presents a new trace signal selection technique which has comparable or better quality than simulation-based while it has a fast runtime, comparable to the metric-based techniques.