Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Advanced techniques for RTL debugging
Proceedings of the 40th annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Reap what you sow: spare cells for post-silicon metal fix
Proceedings of the 2008 international symposium on Physical design
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
An embedded infrastructure of debug and trace interface for the DSP platform
Proceedings of the 45th annual Design Automation Conference
On automated trigger event generation in post-silicon validation
Proceedings of the conference on Design, automation and test in Europe
In-band cross-trigger event transmission for transaction-based debug
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Integrated circuit security: new threats and solutions
Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Spare-cell-aware multilevel analytical placement
Proceedings of the 46th Annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Programmable logic core enhancements for high-speed on-chip interfaces
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Enabling efficient post-silicon debug by clustering of hardware-assertions
Proceedings of the Conference on Design, Automation and Test in Europe
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Low-cost design for repair with circuit partitioning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Proceedings of the 48th Design Automation Conference
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
Proceedings of the 48th Design Automation Conference
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Bridging pre- and post-silicon debugging with BiPeD
Proceedings of the International Conference on Computer-Aided Design
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deterministic Replay Using Global Clock
ACM Transactions on Architecture and Code Optimization (TACO)
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Machine learning-based anomaly detection for post-silicon bug diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RATS: restoration-aware trace signal selection for post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging reconfigurability to raise productivity in FPGA functional debug
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.