A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Functional coverage measurements and results in post-Silicon validation of Core2 duo family
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Quick detection of difficult bugs for effective post-silicon validation
Proceedings of the 49th Annual Design Automation Conference
Bridging pre- and post-silicon debugging with BiPeD
Proceedings of the International Conference on Computer-Aided Design
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging accelerated simulation for floating-point regression
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Intel's move towards the SoC paradigm comes with a compelling requirement for shorter time-to-market. To address that, we need to make both pre and post silicon validation more efficient. In this paper we focus on post-si functional validation, which consumes an increasing share of the overall product development timeline. We present a coherent Pre-to-Post workflow that aims to improve productivity of post-si validation and debug by proper investment in design for debug/validation (DFx) and in test development during pre-si stages. In this workflow, a central transactions and events definition repository serves as the backbone across pre-Si and post-Si activities. The transaction spec guides DFx work in pre-Si as well as test suite preparation in order to make the post-Si validation work productive. Usage of micro-architectural events and transactions raises the level of abstraction, and can help in getting better productivy, manageability, reusability, and less error prone Post-Si validation work.