Model checking
FPgen - a test generation framework for datapath floating-point verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Synthesis of system verilog assertions
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
A probabilistic alternative to regression suites
Theoretical Computer Science
Constraint-based random stimuli generation for hardware verification
IAAI'06 Proceedings of the 18th conference on Innovative applications of artificial intelligence - Volume 2
Simulation-Based Verification of Floating-Point Division
IEEE Transactions on Computers
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Advances in simultaneous multithreading testcase generation methods
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
Hardware/software co-designed accelerator for vector graphics applications
SASP '11 Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Accelerated simulation (acceleration) platforms play a pivotal role in the verification of today's complex designs. Currently, acceleration is used with either adapted pre-silicon tools or post-silicon tools. We present a novel acceleration-only tool, which enables a fast and efficientmethodology for floatingpoint regression. We overcome the lack of test-bench in this environment through self-checking.