Synthesis of system verilog assertions

Authors:
Sayantan Das;Rizi Mohanty;Pallab Dasgupta;P. P. Chakrabarti
Affiliations:
Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India
Venue:
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Year:
2006

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Abstract

In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog language integrates the specification of assertions with the hardware description. In this paper we show that there are several compelling reasons for synthesizing assertions in hardware, and present an approach for synthesizing System Verilog Assertions (SVA) in hardware. Our method investigates the structure of SVA properties and decomposes them into simple communicating parallel hardware units that together act as a monitor for the property. We present a tool that performs this synthesis, and also show that the chip area required by the monitors for a industry standard ABV IP for the ARM AMBA AHB protocol is quite modest.