Introduction to Automata Theory, Languages and Computability
Introduction to Automata Theory, Languages and Computability
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Assertion-Based Design
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Synthesis of system verilog assertions
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
LTL Path Checking Is Efficiently Parallelizable
ICALP '09 Proceedings of the 36th Internatilonal Collogquium on Automata, Languages and Programming: Part II
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
Proceedings of the 47th Design Automation Conference
Validating assertion language rewrite rules and semantics with automated theorem provers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Enabling efficient post-silicon debug by clustering of hardware-assertions
Proceedings of the Conference on Design, Automation and Test in Europe
Fault tolerant system design and SEU injection based testing
Microprocessors & Microsystems
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems and Software
Proceedings of the International Conference on Computer-Aided Design
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Assertion-based verification with languages such as PSL is gaining in importance. From assertions, one can generate hardware assertion checkers for use in emulation, simulation acceleration and silicon debug. We present techniques for checker generation of the complete set of PSL properties, including all variants of operators, both strong and weak. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations that can not be done in a modular approach where subcircuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is derived for other operators. Automata splitting is introduced for an efficient implementation of the eventually! operator.