DAC '98 Proceedings of the 35th annual Design Automation Conference
The temporal logic of branching time
POPL '81 Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Assertion-based verification turns the corner
IEEE Design & Test
Assertion-Based Design
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
Block-based Schema-driven Assertion Generation for Functional Verification
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic generation of complex properties for hardware designs
Proceedings of the conference on Design, automation and test in Europe
Rigel: an architecture and scalable programming interface for a 1000-core accelerator
Proceedings of the 36th annual international symposium on Computer architecture
Novel test detection to improve simulation efficiency: a commercial experiment
Proceedings of the International Conference on Computer-Aided Design
Word level feature discovery to enhance quality of assertion mining
Proceedings of the International Conference on Computer-Aided Design
Generating concise assertions with complete coverage
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Formal methods for ranking counterexamples through assumption mining
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automatic generation of compact formal properties for effective error detection
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Diagnosing root causes of system level performance violations
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of System Level Assertions from Transaction Level Models
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
We present GoldMine, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. We present results of using GoldMine for assertion generation of the RTL of a 1000-core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.