C4.5: programs for machine learning
C4.5: programs for machine learning
Learning with Kernels: Support Vector Machines, Regularization, Optimization, and Beyond
Learning with Kernels: Support Vector Machines, Regularization, Optimization, and Beyond
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
Kernel Methods for Pattern Analysis
Kernel Methods for Pattern Analysis
Subgroup Discovery with CN2-SD
The Journal of Machine Learning Research
A Framework for Constrained Functional Verification
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
Functional test selection based on unsupervised support vector analysis
Proceedings of the 45th annual Design Automation Conference
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Learning microarchitectural behaviors to improve stimuli generation quality
Proceedings of the 48th Design Automation Conference
Online selection of effective functional test programs based on novelty detection
Proceedings of the International Conference on Computer-Aided Design
Microprocessor Verification via Feedback-Adjusted Markov Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data mining in design and test processes: basic principles and promises
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Simulation knowledge extraction and reuse in constrained random processor verification
Proceedings of the 50th Annual Design Automation Conference
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Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.