Decomposing constraint satisfaction problems using database techniques
Artificial Intelligence
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On the Desirability of Acyclic Database Schemes
Journal of the ACM (JACM)
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
A Comparison of Structural CSP Decomposition Methods
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
Simplifying Boolean constraint solving for random simulation-vector generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Constraint synthesis for environment modeling in functional verification
Proceedings of the 40th annual Design Automation Conference
Finding composition trees for multiple-valued functions
ISMVL '97 Proceedings of the 27th International Symposium on Multiple-Valued Logic
A new decomposition method for multilevel circuit design
EURO-DAC '91 Proceedings of the conference on European design automation
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functional test selection based on unsupervised support vector analysis
Proceedings of the 45th annual Design Automation Conference
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic detection of software defects: an industrial experience
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic assertion extraction via sequential data mining of simulation traces
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online selection of effective functional test programs based on novelty detection
Proceedings of the International Conference on Computer-Aided Design
Novel test detection to improve simulation efficiency: a commercial experiment
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
We describe a framework for constrained simulation-vector generationin an industry setting. The framework consists of two keycomponents: the constraint compiler and the vector generator. Theconstraint compiler employs various techniques, including prioritization,partitioning, extraction, and decomposition, to minimize theinternal representation of the constraints, and thus the complexityof constraint solving. The vector generator then uses the compileddata together with input biasing to generate random simulation vectors.Constraints and input biases are treated in a unified manner inthe vector generator. Although there are many alternative ways ofgenerating vectors from constraints, the framework uniquely suits apractical constrained verification environment because of its abilityto handle complicated constraints and its seamless treatment of constraintsand biases. We illustrate the effectiveness of the frameworkwith real examples from commercial designs.