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Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Constructing Small Sample Spaces Satisfying Given Constants
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AVPGEN—a test generator for architecture verification
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High performance BDD package by exploiting memory hierarchy
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Constraint Slving for Test Case Generation
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Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
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Functional test generation for behaviorally sequential models
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Nuts and bolts of core and SoC verification
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High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
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Executable Protocol Specification in ESL
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Simplifying Boolean constraint solving for random simulation-vector generation
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Constraint synthesis for environment modeling in functional verification
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Checking satisfiability of a conjunction of BDDs
Proceedings of the 40th annual Design Automation Conference
Generating random solutions for constraint satisfaction problems
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Fault Models and Test Generation for Hardware-Software Covalidation
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A Framework for Constrained Functional Verification
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Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
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Functional test generation based on word-level SAT
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Stimulus generation for constrained random simulation
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Application of Formal Word-Level Analysis to Constrained Random Simulation
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Optimal constraint-preserving netlist simplification
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Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra
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A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints
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Interpolating functions from large Boolean relations
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Automatic constraint generation for guided random simulation
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Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulation to a legal input space, while input biasing, which can be considered as a probabilistic constraint, makes it easier to cover interesting “corner” cases. In this paper, we propose to use constraints and biasing to form a simulation environment instead of using an explicit testbench in hierarchical functional verification. Both constraints and input biasing can depend on the state of the design and thus are very expressive in modeling the environment. We present a novel method that unifies the handling of constraints and biasing via the use of Binary Decision Diagrams (BDDs). The distribution of input vectors under the effect of constraints and input biasing are determined by what we refer to as the constrained probabilities. A BDD representing the constraints is first built, then an algorithm is applied to bias the branching probabilities in the BDD. During simulation, this annotated BDD is used to generate input vectors whose distribution match their predetermined constrained probabilities. The simulation generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe a partitioning method to minimize the size of BDDs used in simulation generation. Our techniques were used in the verification of a set of commercial designs; experimental results demonstrated their effectiveness.