A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Exhaustive simulation need not require an exponential number of tests
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
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Discrete Mathematics
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Communications of the ACM
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CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
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IEEE Design & Test
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FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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This paper addresses simulation-based verification of high-level [algorithmic, behavioral, or register-transfer level (RTL)] descriptions of arithmetic datapaths that perform polynomial computations over finite word-length operands. Such designs are typically found in digital signal processing (DSP) for audio/video and multimedia applications; where the wordlengths of input and output signals (bit-vectors) are predetermined and fixed according to the desired precision. Initial descriptions of such systems are usually specified as MATLAB/C code. These are then automatically translated into behavioral/RTL descriptions for subsequent hardware synthesis. In order to verify that the initial MATLAB/C model is bit-true equivalent to the translated RTL, how many simulation vectors need to be applied? This paper derives some important results that show that exhaustive simulation is not necessary to prove/disprove their equivalence. To derive these results, we model the datapath computations as polynomial functions over finite integer rings of the form Z2m, where m corresponds to the bit-vector word-length. Subsequently, by exploring some number theoretic and algebraic properties of these rings, we derive an upper bound on the number of simulation vectors required to prove equivalence or to identify bugs. Moreover, these vectors cannot be arbitrarily generated. We identify exactly those vectors that need to be simulated. Experiments are performed within practical computer-aided design (CAD) settings to demonstrate the validity and applicability of these results.