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IEEE Transactions on Computers
Gro¨bner bases: a computational approach to commutative algebra
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On polynomial functions from Zn1×Zn2× &ldots;×Znr to Zm
Discrete Mathematics
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DAC '98 Proceedings of the 35th annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Journal of Signal Processing Systems
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This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bit-vectors that have differing bit-widths. Such designs are found in many DSP applications where the widths of input and output bit-vectors are dictated by the desired precision. A bit-vector of size n can represent integer values from 0 to 2n -- 1; i. e. integers reduced modulo 2n. Therefore, to verify bit-vector arithmetic over multiple word-length operands, we model the RTL datapath as a polynomial function from Z2n1 XZ 2n2 X . . . X . . . Z2nd to Z2m. Subsequently, RTL equivalence f ≡ g is solved by proving whether (f -- g) ≡ 0 over such mappings. Exploiting concepts from number theory and commutative algebra, a systematic, complete algorithmic procedure is derived for this purpose. Experimentally, we demonstrate how this approach can be applied within a practical CAD setting. Using our approach, we verify a set of arithmetic datapaths at RTL where contemporary approaches prove to be infeasible.