Theory of linear and integer programming
Theory of linear and integer programming
Experiences with constraint-based array dependence analysis
Experiences with constraint-based array dependence analysis
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
An Automata-Theoretic Approach to Presburger Arithmetic Constraints (Extended Abstract)
SAS '95 Proceedings of the Second International Symposium on Static Analysis
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Coverage-directed validation of hardware models
Coverage-directed validation of hardware models
Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An efficient finite-domain constraint solver for circuits
Proceedings of the 41st annual Design Automation Conference
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Structural search for RTL with predicate learning
Proceedings of the 42nd annual Design Automation Conference
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
Word level functional coverage computation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
MathSAT: Tight Integration of SAT and Mathematical Decision Procedures
Journal of Automated Reasoning
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Temporalization of Probabilistic Propositional Logic
LFCS '09 Proceedings of the 2009 International Symposium on Logical Foundations of Computer Science
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT($\mathcal{LIA}$)
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Fast and Accurate Bounds on Linear Programs
SEA '09 Proceedings of the 8th International Symposium on Experimental Algorithms
Cuts from Proofs: A Complete and Practical Technique for Solving Linear Inequalities over Integers
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Annals of Mathematics and Artificial Intelligence
Encoding RTL Constructs for MathSAT: a Preliminary Report
Electronic Notes in Theoretical Computer Science (ENTCS)
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Constraint integer programming: a new approach to integrate CP and MIP
CPAIOR'08 Proceedings of the 5th international conference on Integration of AI and OR techniques in constraint programming for combinatorial optimization problems
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cuts from proofs: a complete and practical technique for solving linear inequalities over integers
Formal Methods in System Design
A scalable method for solving satisfiability of integer linear arithmetic logic
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
From propositional satisfiability to satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
A progressive simplifier for satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
URBiVA: uniform reduction to bit-vector arithmetic
IJCAR'10 Proceedings of the 5th international conference on Automated Reasoning
Approximating predicate images for bit-vector logic
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Conflict analysis in mixed integer programming
Discrete Optimization
Constraint satisfaction over bit-vectors
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
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Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.