Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Functional Test Generation using Constraint Logic Programming
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
A fast pseudo-boolean constraint solver
Proceedings of the 40th annual Design Automation Conference
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Approximating predicate images for bit-vector logic
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) description of the arithmetic circuit parts and the property. The ABL description can easily be provided by the front-end of an RTL property checker. The proposed normalization greatly simplifies the SAT instances to be solved for arithmetic circuit verification. Our approach has been applied successfully to verify the integer pipeline of an industrial microprocessor with advanced DSP capabilities.