Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Automatically validating temporal safety properties of interfaces
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
An efficient finite-domain constraint solver for circuits
Proceedings of the 41st annual Design Automation Conference
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Predicate Abstraction of ANSI-C Programs Using SAT
Formal Methods in System Design
Word level predicate abstraction and refinement for verifying RTL verilog
Proceedings of the 42nd annual Design Automation Conference
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Refinement strategies for verification methods based on datapath abstraction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
EXE: automatically generating inputs of death
Proceedings of the 13th ACM conference on Computer and communications security
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Cogent: accurate theorem proving for program verification
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Shortening the verification cycle with synthesizable abstract models
Proceedings of the 46th Annual Design Automation Conference
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Most formal verification tools on the market convert a high-level register transfer level (RTL) design into a bit-level model. Algorithms that operate at the bit-level are unable to exploit the structure provided by the higher abstraction levels, and thus, are less scalable. This tutorial surveys recent advances in formal verification using high-level models. We present word-level verification with predicate abstraction and satisfiability modulo theories (SMT) solvers. We then describe techniques for term-level modeling and ways to combine word-level and term-level approaches for scalable verification.