Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Model checking
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Syntactic Program Transformations for Automatic Abstraction
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Successive Approximation of Abstract Transition Relations
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Predicate Abstraction of ANSI-C Programs Using SAT
Formal Methods in System Design
SATABS: SAT-Based predicate abstraction for ANSI-C
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Reconsidering CEGAR: Learning Good Abstractions without Refinement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Verification of SpecC using predicate abstraction
Formal Methods in System Design
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
Hybrid CEGAR: combining variable hiding and predicate abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Decision Procedures for the Grand Challenge
Verified Software: Theories, Tools, Experiments
Reveal: A Formal Verification Tool for Verilog Designs
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Representing and Validating Digital Business Processes
Advances in Web Semantics I
The synergy of precise and fast abstractions for program verification
Proceedings of the 2009 ACM symposium on Applied Computing
Complexity and Algorithms for Monomial and Clausal Predicate Abstraction
CADE-22 Proceedings of the 22nd International Conference on Automated Deduction
A Framework for Compositional Verification of Multi-valued Systems via Abstraction-Refinement
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VCEGAR: Verilog counterexample guided abstraction refinement
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Local abstraction-refinement for the mu-calculus
Proceedings of the 14th international SPIN conference on Model checking software
Tighter integration of BDDs and SMT for predicate abstraction
Proceedings of the Conference on Design, Automation and Test in Europe
Finding first-order minimal unsatisfiable cores with a heuristic depth-first-search algorithm
IDEAL'11 Proceedings of the 12th international conference on Intelligent data engineering and automated learning
Property-specific sequential invariant extraction for SAT-based unbounded model checking
Proceedings of the International Conference on Computer-Aided Design
EverLost: a flexible platform for industrial-strength abstraction-guided simulation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Approximating predicate images for bit-vector logic
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Towards efficient MUS extraction
AI Communications - 18th RCRA International Workshop on “Experimental evaluation of algorithms for solving problems with combinatorial explosion”
Word level feature discovery to enhance quality of assertion mining
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not relevant to the property. However, localization reduction fails to reduce the size of the model if the property actually depends on most of the latches. This paper proposes to use predicate abstraction for verifying RTL Verilog, a technique successfully used for software verification. The main challenge when using predicate abstraction is the discovery of suitable predicates. We propose to use weakest preconditions of Verilog statements in order to obtain new predicates during abstraction refinement. This technique has not been applied to circuits before. On benchmarks taken from an industrial microprocessor, we successfully verified safety properties with more than 32,000 latches in the cone of influence. We compare the performance of our technique with a modern model checker that implements localization reduction.