Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Automatically validating temporal safety properties of interfaces
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
RTL c-based methodology for designing and verifying a multi-threaded processor
Proceedings of the 39th annual Design Automation Conference
A Discipline of Programming
The formal execution semantics of SpecC
Proceedings of the 15th international symposium on System Synthesis
An improvement in formal verification
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Parameterized Verification of Multithreaded Software Libraries
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
MOCHA: Modularity in Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
High Level Verification of Control Intensive Systems Using Predicate Abstraction
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Summarizing procedures in concurrent programs
Proceedings of the 31st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Predicate Abstraction of ANSI-C Programs Using SAT
Formal Methods in System Design
Efficient Verification of Sequential and Concurrent C Programs
Formal Methods in System Design
Dynamic partial-order reduction for model checking software
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Word level predicate abstraction and refinement for verifying RTL verilog
Proceedings of the 42nd annual Design Automation Conference
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Context-Bounded model checking of concurrent software
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SATABS: SAT-Based predicate abstraction for ANSI-C
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Bounded model checking of concurrent programs
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Cogent: accurate theorem proving for program verification
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic model checking for asynchronous boolean programs
SPIN'05 Proceedings of the 12th international conference on Model Checking Software
A practical and complete approach to predicate refinement
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the formal verification of component-based embedded operating systems
ACM SIGOPS Operating Systems Review
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Languages such as SystemC or SpecC offer modeling of hardware and whole system designs at a high level of abstraction. However, formal verification techniques are widely applied in the hardware design industry only for low level designs, such as a netlist or RTL. The higher abstraction levels offered by these new languages are not yet amenable to rigorous, formal verification. This paper describes how to apply predicate abstraction to SpecC system descriptions. The technique supports the concurrency constructs offered by SpecC. It models the bit-vector semantics of the language accurately, and can be used both for property checking and for checking refinement together with a traditional low-level design given in Verilog.