RTL c-based methodology for designing and verifying a multi-threaded processor

Authors:
Luc Sèmèria;Renu Mehra;Barry Pangrle;Arjuna Ekanayake;Andrew Seawright;Daniel Ng
Affiliations:
Synopsys, Inc.;Synopsys, Inc.;Synopsys, Inc.;Synopsys, Inc.;O-In Design Automation, Inc.;Broadcom, Inc.
Venue:
Proceedings of the 39th annual Design Automation Conference
Year:
2002

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Abstract

A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.