Embedded tutorial: formal equivalence checking between system-level models and RTL

Authors:
A. Koelbl;Yuan Lu;A. Mathur
Affiliations:
Synopsys, Inc., Mountain View, CA, USA;Michigan Univ., Ann Arbor, MI, USA;Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

A rigorous system-level model (SLM) for a hardware design project is extremely important, often critical. Such a functional model not only defines the architect's ideas but also builds a precise foundation for both hardware designers and verification engineers. The key uses of SLMs are: architecture validation; performance modeling and architectural trade-off; platforms for software development and verification; and functional reference model. In this tutorial, we discuss how to formally verify sequential equivalence between SLMs and RTL, for both timed and untimed models. First, we provide a formal definition of the sequential equivalence. Then we discuss various formal verification technology that enables such practice in real designs.